Leverage Rhapsody to generate hardware specifications from your SysML models.

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SysML Synthesis to SystemC

SysML Synthesis to SystemC

SysML in Rhapsody is untimed and sequential, so how does MDGen for SystemC generate cycle accurate, concurrent descriptions in SystemC?

MDGen for SystemC bridges the execution semantics by its sophisticated synthesis engine. MDGen for SystemC’s technology coordinates the parallel execution and guarantees preservation of transaction order, something that a naïve translation cannot. SysML structure is mapped to SystemC modules, state machine behavior is mapped to SystemC component structures, and AND-state concurrency is mapped to multiple SystemC processes within a block. Also, timing and hardware specific artifacts such as lock/reset lines are generated automatically.

Hardware/Software Workflow

Hardware/Software Workflow

In the system workflow at left, requirements are captured in DOORS, then imported into Rhapsody. Rhapsody can automatically generate software, but not hardware descriptions. The hardware models are needed to work with tools for architectural analysis/optimization, hardware implementation and software simulation and validation. MDGen for SystemC addresses this automation gap in the flow.

Who benefits from MDGen for SystemC?

Embedded software developers who need to start their development before the target hardware is available, and hardware architects that wish to tie their designs into an overall system model for traceability and analysis.

What can MDGen for SystemC do for you?


Create optimum balance with architectural trade-offs in speed, power, functionality, and cost.


Leverage SysML executable models and validation.


Reduce errors introduced through manual SystemC creation.

Where MDGen for SystemC Excels:

MDGen for SystemC can automate the architectural exploration of many hardware/software designs, generate synthesizable SystemC implementations, and create cycle-accurate test benches.

Ask Us Anything About MDGen for SystemC